There are disclosed the data holding circuits for preventing destruction of the stored data in Japanese Patent Laid-Open Publication No. 55-23583, Utility Model Laid-Open Publication No. 57-110799, Patent Laid-Open Publication No. 58-94200, Utility Model Laid-Open Publication No. 59-84642, Patent Laid-Open Publication No. 61-283939, Utility Model Laid-Open Publication No. 62-53738, Patent Laid-Open Publication No. 63-15346 and Utility Model Laid-Open Publication No. 63-44296, an example which will be described with reference to FIG. 1.
A data protection circuit 10 comprises an inverter 1 and a 2 input NAND gate 12. One input terminal 12a of the 2 input NAND gate 12 receives a chip select signal CS from a power supply monitoring circuit 20 and another input terminal 12b receives an external write control signal WR from a processor 30 by way the inverter 11. Accordingly, an output of the 2 input NAND gate 12, i.e. a signal level of an internal write control signal W as an output of the data protection circuit 10 conforms to a high (H) or a low (L) signal of the external write control signal WR in the case that the chip select signal CS is a high (select) level (hereinafter referred to as H level) and is kept always at H level irrespective of the level of the external write control signal WR in the case that the chip select signal CS is low (nonselect) level (hereinafter referred to as L level).
The data holding circuit 40 receives the internal write signal W so that it becomes in a data write enable state in the case that the internal write control signal W is at H level and in a data write inhibiting state in the case that the internal write control signal W is at L level. The data holding circuit 40 receives a voltage V.sub.m from the main power supply 51 or V.sub.b from the backup power supply 52 by way of the power supply selector switch 50, hence it can hold the data on the basis of the voltage V.sub.b from a backup power supply 52 even if the main power supply 51 is broken. The voltage from the output 53 of the selector switch 50 is also supplied to the data protection circuit 10 and the power supply monitoring circuit 20. Whereupon, the voltage V.sub.m provided by the main power supply 51 is supplied to the processor 30 which is monitored by the power supply monitoring circuit 20.
An operation of the circuit set forth above will be described with reference to FIG. 2.
The power supply monitoring circuit 20 causes the chip select signal CS to be at L level when it detects that the voltage V.sub.m of the main power supply 51 reaches a first predetermined voltage V.sub.m1. Inasmuch as the internal write control signal W as the output of the data protection circuit 10 is always kept at H level, the data holding circuit 40 is in the write inhibiting state.
The power supply monitoring circuit 20 drives the selector switch 50 to switch the main power supply 51 to the backup power supply 52 when it detects that the voltage V.sub.m of the main power supply 51 is less than a second predetermined voltage V.sub.m2.
When the main power supply 51 is recovered, the power supply monitoring circuit 20 detects that the voltage V.sub.m of the main power supply 51 exceeds the second predetermined voltage V.sub.m2 for thereby driving the selector switch 50 to switch to the main power supply 51 from the backup power supply 52, and thereafter provide the chip select signal CS of H level after the lapse of time t1.
With the operation set forth above, according to the circuit as illustrated in FIG. 1, the voltage exceeding the voltage V.sub.b is always supplied to the data holding circuit 40 from the output 53 of the selector switch 50 as illustrated in FIG. 2 so that the circuit can inhibit the data holding circuit 40 from writing the data therein from the time when the data holding circuit 40 detects that the voltage V.sub.m of the main power supply 51 is less than the first predetermined voltage V.sub.m1 up to the time when the voltage V.sub.m increases to the voltage sufficient to normally drive the processor (operation assurance voltage).
However, inasmuch as the conventional data holding circuit can not detect the breakage of the main power supply until the voltage V.sub.m of the main power supply 51 is reduced to the first predetermined voltage V.sub.m1, the data holding circuit 40 becomes in a state of write enable state when the processor 30 provides the external write control signal WR of L level during the period from the time when the main power supply is broken up to the time when the voltage V.sub.m of the main power supply is less than the first predetermined voltage V.sub.m1 (power supply unstable period). At this state, there is a likelihood that the data is destructive when the data is written in the data holding circuit 40. Since the operation assurance voltage of the processor 30 is generally higher than the first predetermined voltage V.sub.m1, the processor 30 is not in a normal sate and liable to provide the erroneous write control signal during the power supply unstable period. Hence, the conventional holding circuit is deemed to be insufficient to protect the data with assurance.